In this presentation, the experience so far gained by the authors in their research is reported; from mere off-line simulation to FPGA-based hardware-in-the-loop (HIL) emulation of a sensorless first-order sliding-mode controller for a doubly-fed induction generator (DFIG).
Concerning methodology, aiming at accelerating the execution of off-line simulations as much as possible, the models we build in Simulink are almost exclusively based on S-function blocks programmed in C language (C-MEX). Moreover, in the case of power converters, we typically used to regard them as ideal, or represent them in simplified form through approximate models considering mean values. Even though those approximations may be applicable to converters commanded via field-oriented control (FOC), algorithms such as direct power control (DPC) or first-order sliding mode control (1-SMC) demand the use of models considering the commutations of the power converter’s transistors.

Nevertheless, when incorporating converter models representing those commutations, the execution of pure off-line simulations slows down considerably. In addition, due above all to latency and jitter phenomena, simulation results are no longer reliable, and may even become manifestly incorrect. It is therefore necessary to have a trustworthy tool available, which allows not only facing the analysis and design tasks with confidence, but also speeding up simulations.

A particular real-time simulation case, corresponding to the sensorless 1-SMC of a DFIG described in [1], is presented. A full-detail virtual prototype of a 660-kW DFIG, including the rotor-side converter (RSC), is implemented via a C-MEX-type S-function running on a computational node —CPU— of the Opal-RT eMEGAsim OP4500 F11-13 platform. The digital MRAS —Model Reference Adaptive System— observer in charge of estimating the rotor electrical speed and position, required as inputs to the 1-SMC, is also implemented through a C-MEX-type S-function running on another CPU of the eMEGAsim platform. A third CPU accommodates the 1-SMC algorithm itself, which is again programmed as a C-MEX-type S-function. Results relating to synchronization and subsequent connection of the DFIG to the grid, convergence of the MRAS observer, and generation optimization under wind gusts are provided, together with time-related parameters assessing real-time performance.

Given that the aforementioned 1-SMC algorithm operates at a particularly high sample rate of 40 kHz, a field programmable gate array (FPGA) might be considered as a natural means to implement it, if a final product to be adopted by industry was required. Currently, the authors of this presentation and engineers from Opal-RT collaborate on the XSG-based development of the entire 1-SMC algorithm on a Virtex-II Pro series FPGA by Xilinx, embedded in the eMEGAsim platform. The objective is to perform HIL emulation by replacing the 1-SMC algorithm running on a CPU with that programmed on the FPGA. This way, it would be proved that the proposed 1-SMC is not just a theoretical concept that is difficult to realize, but a practical algorithm that could be industrially implemented on a commercially available FPGA.

[1] Ana Susperregui, G. Tapia, I. Zubia, and J. X. Ostolaza, “Sliding-mode control of doubly-fed generator for optimum power curve tracking,” IET Electronics Letters, vol. 46, no. 2, pp. 126–127, January 2010.

Author(s): Gerardo Tapia,
Narrator: Gerardo Tapia,

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