Very-high Speed Control of an FPGA-based Finite-Element-Analysis Permanent Magnet Synchronous Virtual Motor Drive System

Publication date : Oct 2008
Paper File : Paper_IECON_2008_Opal-RT_Dufour.pdf



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Abstract

Presented in this paper are the results of tests involving high-speed closed-loop control of a virtual permanent magnet synchronous motor (PMSM) drive implemented on a field-programmable gate array (FPGA) card, connected to an external controller. Three types of motor drive models are actually implemented on the FPGA card of the RT-LAB based real-time simulator used: a Park (d-q) model along with two different implementations of Finite Element Analysis (FEA) based models. The first FEA model, previously published, is an FPGA implementation of a FEA model with an inductance calculation routine running on an associated CPU of the real-time simulator. The second FEA model has its inductance routine coded in the FPGA. One of the main objectives of the paper will be to compare the performance of the two FEA models. By virtue of the faster, FPGA-located, inductance routine update rate of the new model, it is expected that its precision at very high speed will be greater than the previous model, which was shown to be limited to 400 Hz electric frequency. The tests will be made in closed-loop mode for current control mode, at fixed speed, and also in speed control model. The controller is designed using Rapid Control Prototyping (RCP) methodology based on Simulink, and is also run on a second RTLAB real-time simulator. The controller and the motor drive are interfaced through I/O channels only, not unlike a real motor drive: Analog I/O signals for motor current and resolver signals, and Digital I/O for the IGBT gate pulse signals and quadrature encoder signals. In contrast to a previously published work, the resolver signal decoding will be made with an Xilink System Generator (XSG) implementation of a Synchro/Resolver-To-Digital converter. The FPGA-based motor model is designed with the Xilinx System Generator (XSG) blockset with no HDL hand coding. Both motor models compute motor currents using a phasedomain algorithm solver that can take into account the instantaneous variation of inductance and non-sinusoidal induced voltage. The FEA-type model uses inductance and Back-EMF profiles computed with JMAG-RT. The d-q model use sinusoidal induced Back-EMF voltage and phase inductance values computed from Ld and Lq using the well-known Park transformation. A 3-phase IGBT inverter implemented in the FPGA chip drives the PMSM machine. The motor controller is a PWM vector controller designed in Simulink and running at a sample time of 50 microseconds. It is implemented on an RT-LAB simulator using standard Opal-RT FPGA-based I/O cards for Analog Input capture and PWM generation. The paper will present results from the closed-loop control of the PMSM drive in both current control and speed control modes and discuss the advantages of using such a virtual test bench for motor drives.

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