Thyristor-based SVC
The real-time simulation of an SVC (static VAR compensator) was made on 2 independent RT�LAB simulators. The plant part, which includes the main power system source, transformer, a thyristor controlled reactor, and 3–thyristor, switched capacitor banks, was made on a dual-Xeon-based RT�LAB simulator. The controller part, which includes a PI compensator, synchronization unit, and thyristor firing pulse units, was made with a Pentium-M-based RT�LAB simulator. Both simulators were equipped with the necessary I/O to interface to each other: The controller had analog input to read the power system voltages and digital output to fire the thyristor. The plant simulator had complimentary I/O (analog output and digital inputs).
The demo implements a special MOV model to demonstrate capacitor protection, and uses stublines to effectively and accurately decouple each TSC (Thyristor Switched Capacitor) bank, allowing full precomputation of circuit modes by ARTEMIS.
System Configuration |
|
|---|---|
| Application Package | AD-GRID-03 |
| CPU Type | dual Intel® Core 2.3 GHz |
| Number of CPUs | 2 |
| Time Step | 50µs |
| Minimum Time Step | 16µs |
| Time Factor | 6 |





