OP5000 I/O Adapter for Xilinx Virtex5 ML506 Module
FPGA Co-simulation using Virtex 5 and ML506 board |
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Software Requirements
- RT-LAB 8.3.x and over
- Matlab R2007b or R2008a with RTW
- Xilinx ISE 10.1 SP3
- Xilinx System Generator 10.1.03
On board Mezzanine I/O Configuration
- Option 1
- 2 slots of 16 Analog I/O (can be 16in/16in, 16in/16out, 16out/16out)
- 22 Digital Reconfigurable I/O (11in and 11out)
- Option 2
- 70 Digital Reconfigurable I/O
Features
Link to Xilinx Web Page.
http://www.xilinx.com/products/devkits/HW-V5-ML506-UNI-G.htm
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