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ML506 - Integrated FPGA Development System

Enclosure and I/O Signal Conditioning for the ML506 Development Board.

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Specifications

ML506 Virtex5 Developement Board
Two Type B mezzanines for Signal Conditioning (16 DAC or 16 ADC per mezannine)
Up to 70 3.3V Buffered Digital I/O Line connected directly to Virtex5 FPGA

Operation Mode

Stand Alone (FPGA Programming using JTag)
HIL Mode (Connected to a Real-Time HIL Target usgin PCIx Communication Link)

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	Jun 2011	Floating-Point Engines for the FPGA-Based Real-Time Simulation of Power Electronic Circuits Authors : Christian Dufour, Authors : Jean Mahseredjian, Authors : Jean-Pierre David, Authors : Tarek Ould Bachir Related Event: IPST 2011 - International Conference on Power Transients Abstract : The real-time simulation of power electronic circuits is challenging for several reasons. A PC-based simulation can hardly achieve time-steps below 5-10 μs: this yields a limit on the maximal power electronic switching... Floating-Point Engines for the FPGA-Based.pdf
	Jun 2011	RECONFIGURABLE FLOATING-POINT ENGINES FOR THE REAL-TIME SIMULATION OF PECS: A HIGH-SPEED PMSM DRIVE CASE STUDY Authors : C. Dufour, Authors : J. Bélanger, Authors : J. Mahseredjian, Authors : J.P. David, Authors : T. Ould Bachir Related Event: ELECTRIMACS 2011 Abstract : The real-time simulation of PMSM drives enables thorough testing of control strategies and allows rapid deployment of automotive applications. However, the simulation of power electronic circuits (PECs) in the context of... RECONFIGURABLE FLOATING-POINT ENGINES FOR THE REAL-TIME.pdf

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