Why does the OpMonitor return -1 for the number of overruns?

The overrun will only be detected by the master clock of each model. In software synchronization mode, the master clock is on the Master subsystem (SM_); in hardware synchronization, the master clock is on the subsystem, where the controller block of your Master FPGA is located (i.e. OpCtrl OP5142EX1).

Therefore, only if the OpMonitor is placed in the subsystem that the master clock is present, it can return a meaningful number of overruns. Otherwise, it will return '-1'.