Time-step for the RT-XSG model (FPGA model)

The basic step-size of all RT-XSG models, runing either on OP5142 or OP5130, is 10 nano-seconds, which is enforced by the timer/clock on the FPGA. Therefore, all blocks used in the RT-XSG model have to use a sample time of 10e-9 seconds, or a multiple of this sample time. 

Xilinx Signal Generator, which is used during complation of a bitstream, has a mechanism to check if there is a overflow at this time-step. In other words, it analyzes and guarantees that there is enough time to finish the calculation within10 nano-seconds and also proper delays between blocks. If there is an overflow (like overrun on the CPU model), RT-XSG will report an error during compilation.