FPGA-based simulation of an IGBT H-bridge and RL load

This demo shows the implementation of an IGBT H-bridge, R-L load being simulated in real-time on an FPGA chip, along with pulse-width modulation (PWM).

In this example, the PWM fluctuates between 1k-100kHz. The H-bridge is driven in an open-loop simulation mode by setting the duty cycle in the Console. All parameters of the electrical circuit, including R and L values; DC-link voltage; PWM frequency; dead time and duty-cycle can be directly input by the operator via a user-friendly interface on the host PC.

The latency of the model is essentially equal to the 1 μs conversion rate of the Analog Outputs. The console offers the option of routing the IGBT pulse through the Digital Input and Output (I/O) by an optional, external loop-back connection.

In the present model, the digital I/O are represented as the Front Connector I/O. These I/O can be easily re-routed to the backplan connector, using a single wire in the XSG model.

By connecting the Digital Output to a real H-bridge, one can drive a DC-motor.

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